1. Field of the Invention
The present invention relates to a computer system having a virtual memory configuration. More particularly, it relates to an improvement of address translation-error processing for a virtual memory access to a virtual memory configuration.
2. Description of the Related Art
Virtual memory computer systems are extensively used for alleviating tasks of management of memory areas to be used in user programs. In the virtual memory computer systems, the relationship between logical (virtual) addresses used in the programs and physical (actual) addresses used for actually accessing a main memory is predetermined. A plurality of data, each including the above relationship concerning each unit region of virtual memory and thus known as virtual accessing data in this specification, are stored in the main memory. Upon request of a virtual memory access from a central processor unit (CPU), a corresponding physical address is determined on the basis of the above relationship and an access operation of the physical address to the main memory is effected. In order to speed up the translation (or conversion) from a logical address output from the CPU due to the operation of the program therein to a physical address with reference to the virtual accessing data, an address translation buffer memory (ATB) is provided in the virtual memory computer system. The ATB may be formed by a randomaccess memory (RAM) and has a faster access time than the main memory. However, in general, the memory capacity of the ATB is insufficient for storing all of the virtual accessing data in the main memory. Accordingly, upon request of a virtual memory access from the CPU, corresponding virtual accessing data in the main memory is once transferred to certain memory cells in the ATB, and the address translation is effected in accordance therewith. The above transfer from the main memory to the ATB is effected for a predetermined size of memory, for example, 4 k-bytes. The transferred virtual accessing data remains in the ATB unless deleted due to updating for new virtual accessing data when the ATB is full. Accordingly, subsequent virtual memory accesses of the virtual accessing data in the ATB are improved in the time take. Preferably, virtual accessing data with a high frequency of access requests should be kept in the ATB.
The CPU includes means, which consists of hardware and software, for processing the above virtual memory accessing operation. The software has a halt processing function (or task) which, first, halts the virtual memory accessing operation of the CPU when corresponding virtual accessing data is not in the ATB or corresponding virtual accessing data in the ATB is not suitable for use because of such as invalid data or a parity error, second, transfers correct corresponding virtual access data in the main memory to the ATB, and third, restores the virtual memory accessing operation of the CPU. If the corresponding virtual access data to be transferred to the ATB is not suitable, naturally, the data transfer is not effected and thus the program in the CPU for which the virtual memory accessing operation is halted will be aborted.
A virtual memory computer system including a single CPU, however, suffers from the disadvantage of the low speed of the above halt operation. In the CPU, a multilevel interruption is used for the above halt operation, thus a considerably long time is required for analyzing the interruption. In addition, a plurality of programs are operated in parallel, thus the above halt operation may be disturbed by the operation of the other programs.
In order to overcome the above, virtual memory computer systems further including a sub-CPU for processing the halt operation in addition to a main CPU are known (e.g., Hunter L. Scales III, "Implementing a virtual memory system using the MC 68451 memory management unit", Wescon/81, Professional Program Session Record 9/4, pp. 1 to 8). The main CPU performs tasks of the user programs. The sub-CPU performs the memory management including the above halt processing. The sub-CPU is operable in response to a single significant-level interruption, and thus the halt operation time can be shortened. However, the above virtual memory system still suffers from disadvantages of the troublesome procedure of the halt operation and low speed.